---------------------------------------------------------------------------------
  -- Design Name : Immediate Expand
  -- File Name   : IdImmExp.vhd
  -- Function    : Expands an immediate value to 32b
  -- Authors     : Mirko Francuski  2006/0225
  --               Milos Mihajlovic 2006/0039
  -- School      : University of Belgrade
  --               School for Electrical Engineering
  --               Department for Computer Engineering and Information Theory
  -- Subject     : VLSI Computer Systems
---------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.UserPkg.all;

entity IdImmExp is
  port (
    immType:  in  std_logic_vector(1 downto 0);
    rd:       in  regAddr;
    rs2:      in  regAddr;
    imm11:    in  std_logic_vector(10 downto 0);
    imm:      out word32
  );
end IdImmExp;

architecture behavioral of IdImmExp is
begin
/*
immType:
00:     OPC_STORE | OPC_BEQ | OPC_BEQ | OPC_BNQ | OPC_BLT | OPC_BGT | OPC_BLE | OPC_BGE
01:     OPC_LOAD | OPC_ADDI | OPC_SUBI | OPC_MOVI | OPC_JMP | OPC_JSR
10,11:  OPC_SHL | OPC_SHR | OPC_SAR | OPC_ROL | OPC_ROR
*/


  imm <= std_logic_vector(resize(  signed(rd  & imm11), LEN_WORD)) when immType = "00" else
         std_logic_vector(resize(  signed(rs2 & imm11), LEN_WORD)) when immType = "01" else
         std_logic_vector(resize(unsigned(rs2)        , LEN_WORD));
/*
  process(all)
  begin
    case immType is
      when "00" =>
        imm <= std_logic_vector(resize( signed(rd & imm11), LEN_WORD));

      when "01" =>
        imm <= std_logic_vector(resize( signed(rs2 & imm11), LEN_WORD));

      when "10" | "11" =>
        imm <= std_logic_vector(resize(unsigned(rs2), LEN_WORD));

      when others =>
        imm <= (others => '0');
     end case;
  end process;
*/
end architecture behavioral;